Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture
От | Nathan Bossart |
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Тема | Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture |
Дата | |
Msg-id | aCtej5YeBae9_G0K@nathan обсуждение исходный текст |
Ответ на | Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture (Salvatore Dipietro <dipietro.salvatore@gmail.com>) |
Ответы |
Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture
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Список | pgsql-hackers |
On Tue, May 13, 2025 at 11:37:45AM -0700, Salvatore Dipietro wrote: > On Thu, 1 May 2025 at 14:50, Nathan Bossart <nathandbossart@gmail.com> wrote: >> So... >> >> * The ISB does seem to have a positive effect without commit 3d0b4b1 >> applied. >> >> * With commit 3d0b4b1 applied, removing the ISB seems to have a positive >> effect at high concurrencies. This is especially pronounced in the >> pgbench test. >> >> * With commit 3d0b4b1 applied, removing the ISB doesn't change much at >> lower concurrencies, and there might even be a small regression. >> >> * At mostly lower concurrencies, commit 3d0b4b1 actually seems to regress >> some test_shm_mq tests. Removing the ISB instruction appears to help in >> some cases, but not all. > > Based on your findings Nathan, what is the best way to proceed for this change? > Do we need more validation for it? If yes, which kind? Well, I am confused because your recent message [0] indicated that you saw improvement without the non-locking initial test in TAS_SPIN, which seems to contradict my findings [1]. Could you retry your tests on v18devel? It might also be useful to repeat the tests on a variety of hardware to ensure it's a win across the board. [0] https://postgr.es/m/CAGnuAhXNQXCcS1nCeD6E0Dyfi4Ms-b0sjcm79Y9iMi5WxUqM4g%40mail.gmail.com [1] https://postgr.es/m/aBPsrFbjnrqp3_8S%40nathan -- nathan
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