Re: Misaligned BufferDescriptors causing major performance problems on AMD

On Mon, Jan 26, 2015 at 9:08 PM, Robert Haas <robertmhaas@gmail.com> wrote:
>> Contrary opinions? Robert?
>
> I'm totally OK with further aligning just that one allocation.

Of course, now that I think about it, aligning it probably works
mostly because the size is almost exactly one cache line.  If it were
any bigger or smaller, aligning it more wouldn't help.  So maybe we
should also do something like what LWLocks do, and make a union
between the actual structure and an appropriate array of padding bytes
- say either 64 or 128 of them.

-- 
Robert Haas
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