Re: Latches with weak memory ordering (Re: max_wal_senders must die)

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От Robert Haas
Тема Re: Latches with weak memory ordering (Re: max_wal_senders must die)
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Msg-id AANLkTim8v6EMbA7LtS7AxYTiMPNxhnxuXz3=XYSkD6MW@mail.gmail.com
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Ответ на Re: Latches with weak memory ordering (Re: max_wal_senders must die)  (Tom Lane <tgl@sss.pgh.pa.us>)
Ответы Re: Latches with weak memory ordering (Re: max_wal_senders must die)  (Tom Lane <tgl@sss.pgh.pa.us>)
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On Fri, Nov 19, 2010 at 5:59 PM, Tom Lane <tgl@sss.pgh.pa.us> wrote:
> Robert Haas <robertmhaas@gmail.com> writes:
>> But what about timings vs. random other stuff?  Like in this case
>> there's a problem if the signal arrives before the memory update to
>> latch->is_set becomes visible.  I don't know what we need to do to
>> guarantee that.
>
> I don't believe there's an issue there.  A context swap into the kernel
> is certainly going to include msync.  If you're afraid otherwise, you
> could put an msync before the kill() call, but I think it's a waste of
> effort.

So what DO we need to guard against here?

--
Robert Haas
EnterpriseDB: http://www.enterprisedb.com
The Enterprise PostgreSQL Company


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