Re: Latches with weak memory ordering (Re: max_wal_senders must die)

Robert Haas <robertmhaas@gmail.com> writes:
> But what about timings vs. random other stuff?  Like in this case
> there's a problem if the signal arrives before the memory update to
> latch->is_set becomes visible.  I don't know what we need to do to
> guarantee that.

I don't believe there's an issue there.  A context swap into the kernel
is certainly going to include msync.  If you're afraid otherwise, you
could put an msync before the kill() call, but I think it's a waste of
effort.
        regards, tom lane