On 11/19/2010 04:51 PM, Tom Lane wrote:
> Hm, what do those do exactly?
"Performs a serializing operation on all load-from-memory and
store-to-memory instructions that were issued prior the MFENCE
instruction." [1]
Given the memory ordering guarantees of x86, this instruction might only
be relevant for SMP systems, though.
> Or does "lock xchgb" imply an mfence?
Probably on older architectures (given the name "bus locked exchange"),
but OTOH I wouldn't bet on that still being true. Locking the entire bus
sounds like a prohibitively expensive operation with today's amounts of
cores per system.
Regards
Markus Wanner
[1]: random google hit on 'mfence':
http://siyobik.info/index.php?module=x86&id=170