Re: Latches with weak memory ordering (Re: max_wal_senders must die)

On Friday 19 November 2010 16:51:00 Tom Lane wrote:
> Markus Wanner <markus@bluegap.ch> writes:
> > Well, that certainly doesn't apply to full fences, that are not specific
> > to a particular piece of memory. I'm thinking of 'mfence' on x86_64 or
> > 'mf' on ia64.
> Hm, what do those do exactly?  We've never had any such thing in the
> Intel-ish spinlock asm, but if out-of-order writes are possible I should
> think we'd need 'em.  Or does "lock xchgb" imply an mfence?
Out of order writes are definitely possible if you consider multiple 
processors.
Locked statments like 'lock xaddl;' guarantee that the specific operands (or 
their cachelines) are visible on all processors and are done atomically - but 
its not influencing the whole cache like mfence would.

Andres