Re: Latches with weak memory ordering (Re: max_wal_senders must die)

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От Tom Lane
Тема Re: Latches with weak memory ordering (Re: max_wal_senders must die)
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Msg-id 1162.1290183957@sss.pgh.pa.us
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Ответ на Re: Latches with weak memory ordering (Re: max_wal_senders must die)  (Andres Freund <andres@anarazel.de>)
Ответы Re: Latches with weak memory ordering (Re: max_wal_senders must die)  (Andres Freund <andres@anarazel.de>)
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Andres Freund <andres@anarazel.de> writes:
> Locked statments like 'lock xaddl;' guarantee that the specific operands (or 
> their cachelines) are visible on all processors and are done atomically - but 
> its not influencing the whole cache like mfence would.

Where is this "locking the whole cache" meme coming from?  What we're
looking for has nothing to do with locking anything.  It's primarily
a directive to the processor to flush any dirty cache lines out to
main memory.  It's not going to block any other processors.
        regards, tom lane


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