Re: BUG #15844: MIPS: remove .set mips2 in s_lock.h to fix r6 build

I wrote:
> Sure, the trick would be to not override a (default or specified)
> architecture setting that's higher than mips2.  I was imagining
> using AC_EGREP_CPP() to see if __mips expands to exactly 1.  But
> on reflection, probably a better idea is to just see if asm with
> ll/sc/sync compiles, and add -march=mips2 if not.

Concretely, here's a patch that does it like that.  I've verified
that this builds on my netbsd/gxemul installation.

            regards, tom lane

diff --git a/configure b/configure
index fd61bf6..57ef478 100755
--- a/configure
+++ b/configure
@@ -6900,6 +6900,57 @@ CXXFLAGS="$CXXFLAGS $user_CXXFLAGS"
 BITCODE_CFLAGS="$BITCODE_CFLAGS $user_BITCODE_CFLAGS"
 BITCODE_CXXFLAGS="$BITCODE_CXXFLAGS $user_BITCODE_CXXFLAGS"

+case $host_cpu in
+  mips*)
+    # On MIPS, we must have ll/sc/sync instructions to do spinlocks, but those
+    # do not exist in the long-obsolete MIPS-I architecture.  Annoyingly, many
+    # toolchains still default to emitting MIPS-I code, causing the assembler
+    # to reject these instructions.  If using a gcc workalike, we can fix this
+    # by adding -march=mips2 to CFLAGS; otherwise, you're on your own to
+    # select the right compiler flag or use --disable-spinlocks.
+    if test "$enable_spinlocks" = yes -a x"$GCC" = x"yes"; then
+      { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether assembler supports ll/sc/sync" >&5
+$as_echo_n "checking whether assembler supports ll/sc/sync... " >&6; }
+if ${pgac_cv_have_mips_spinlock_insts+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+register volatile unsigned int *_l = NULL;
+        register int _res, _tmp;
+        __asm__ __volatile__(
+                "       ll      %0, %2      \n"
+                "       sc      %1, %2      \n"
+                "       sync                \n"
+        : "=&r" (_res), "=&r" (_tmp), "+R" (*_l) : : "memory");
+        return _res;
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  pgac_cv_have_mips_spinlock_insts=yes
+else
+  pgac_cv_have_mips_spinlock_insts=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $pgac_cv_have_mips_spinlock_insts" >&5
+$as_echo "$pgac_cv_have_mips_spinlock_insts" >&6; }
+      if test x"$pgac_cv_have_mips_spinlock_insts" = xno; then
+        CFLAGS="$CFLAGS -march=mips2"
+        CXXFLAGS="$CXXFLAGS -march=mips2"
+        BITCODE_CFLAGS="$BITCODE_CFLAGS -march=mips2"
+        BITCODE_CXXFLAGS="$BITCODE_CXXFLAGS -march=mips2"
+      fi
+    fi
+  ;;
+esac
+
 BITCODE_CFLAGS=$BITCODE_CFLAGS

 BITCODE_CXXFLAGS=$BITCODE_CXXFLAGS
diff --git a/configure.in b/configure.in
index 4586a17..e1097aa 100644
--- a/configure.in
+++ b/configure.in
@@ -607,6 +607,38 @@ CXXFLAGS="$CXXFLAGS $user_CXXFLAGS"
 BITCODE_CFLAGS="$BITCODE_CFLAGS $user_BITCODE_CFLAGS"
 BITCODE_CXXFLAGS="$BITCODE_CXXFLAGS $user_BITCODE_CXXFLAGS"

+case $host_cpu in
+  mips*)
+    # On MIPS, we must have ll/sc/sync instructions to do spinlocks, but those
+    # do not exist in the long-obsolete MIPS-I architecture.  Annoyingly, many
+    # toolchains still default to emitting MIPS-I code, causing the assembler
+    # to reject these instructions.  If using a gcc workalike, we can fix this
+    # by adding -march=mips2 to CFLAGS; otherwise, you're on your own to
+    # select the right compiler flag or use --disable-spinlocks.
+    if test "$enable_spinlocks" = yes -a x"$GCC" = x"yes"; then
+      AC_CACHE_CHECK([whether assembler supports ll/sc/sync],
+                     [pgac_cv_have_mips_spinlock_insts],
+      [AC_COMPILE_IFELSE([AC_LANG_PROGRAM([],
+        [register volatile unsigned int *_l = NULL;
+        register int _res, _tmp;
+        __asm__ __volatile__(
+                "       ll      %0, %2      \n"
+                "       sc      %1, %2      \n"
+                "       sync                \n"
+        : "=&r" (_res), "=&r" (_tmp), "+R" (*_l) : : "memory");
+        return _res;])],
+        [pgac_cv_have_mips_spinlock_insts=yes],
+        [pgac_cv_have_mips_spinlock_insts=no])])
+      if test x"$pgac_cv_have_mips_spinlock_insts" = xno; then
+        CFLAGS="$CFLAGS -march=mips2"
+        CXXFLAGS="$CXXFLAGS -march=mips2"
+        BITCODE_CFLAGS="$BITCODE_CFLAGS -march=mips2"
+        BITCODE_CXXFLAGS="$BITCODE_CXXFLAGS -march=mips2"
+      fi
+    fi
+  ;;
+esac
+
 AC_SUBST(BITCODE_CFLAGS, $BITCODE_CFLAGS)
 AC_SUBST(BITCODE_CXXFLAGS, $BITCODE_CXXFLAGS)

diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h
index a9a92de..3af033b 100644
--- a/src/include/storage/s_lock.h
+++ b/src/include/storage/s_lock.h
@@ -614,7 +614,6 @@ tas(volatile slock_t *lock)

     __asm__ __volatile__(
         "       .set push           \n"
-        "       .set mips2          \n"
         "       .set noreorder      \n"
         "       .set nomacro        \n"
         "       ll      %0, %2      \n"
@@ -636,7 +635,6 @@ do \
 { \
     __asm__ __volatile__( \
         "       .set push           \n" \
-        "       .set mips2          \n" \
         "       .set noreorder      \n" \
         "       .set nomacro        \n" \
         "       sync                \n" \