>> 8 апр. 2021 г., в 15:22, Thomas Munro <thomas.munro@gmail.com> написал(а):
>>
> I have one more idea inspired by CPU caches.
> Let's make SLRU n-associative, where n ~ 8.
> We can divide buffers into "banks", number of banks must be power of 2.
> All banks are of equal size. We choose bank size to approximately satisfy user's configured buffer size.
> Each page can live only within one bank. We use same search and eviction algorithms as we used in SLRU, but we only
needto search\evict over 8 elements.
> All SLRU data of a single bank will be colocated within at most 2 cache line.
>
> I did not come up with idea how to avoid multiplication of bank_number * bank_size in case when user configured 31337
buffers(any number that is radically not a power of 2).
We can avoid this multiplication by using gapped memory under SLRU page_statuses, but from my POV here complexity does
notworth possible performance gain.
PFA rebase of the patchset. Also I've added a patch to combine page_number, page_status, and page_dirty together to
touchless cachelines.
Best regards, Andrey Borodin.