Re: Intermediate report for AIX 5L port

Got it.  The AIX compiler apparently feels free to rearrange the
sequence
    proc->lwWaiting = true;    proc->lwExclusive = (mode == LW_EXCLUSIVE);    proc->lwWaitLink = NULL;    if
(lock->head== NULL)        lock->head = proc;    else        lock->tail->lwWaitLink = proc;    lock->tail = proc;
 
    /* Can release the mutex now */    SpinLockRelease_NoHoldoff(&lock->mutex);

into something wherein the SpinLockRelease (which is just "x = 0")
occurs before the last two assignments into the lock structure.
Boo, hiss.  Evidently, on your multiprocessor machine, there may be
another CPU that is able to obtain the spinlock and then read the
un-updated lock values before the stores occur.

Declaring the lock pointer "volatile" seems to prevent this misbehavior.

Personally I'd call this a compiler bug; isn't it supposed to consider
semicolons as sequence points?  I never heard that rearranging the order
of stores into memory was considered a kosher optimization of C code.
        regards, tom lane