Hi,
On 2024-02-12 12:50:12 -0800, Andres Freund wrote:
> On 2024-02-12 13:28:40 -0500, Andrew Dunstan wrote:
> I wonder if this indicates that we are either missing memory barriers
> somewhere or that the memory barriers we end up with on msvc + arm aren't
> correct? Either could explain why the problem doesn't occur when building
> with optimizations.
I think I might have been on to something - if my human emulation of a
preprocessor isn't wrong, we'd end up with
#define S_UNLOCK(lock) \
do { _ReadWriteBarrier(); (*(lock)) = 0; } while (0)
on msvc + arm. And that's entirely insufficient - _ReadWriteBarrier() just
limits *compiler* level reordering, not CPU level reordering. I think it's
even insufficient on x86[-64], but it's definitely insufficient on arm.
Another issue I see is that we have a bunch of code that's dependant on
__aarch64__ being set - but it doesn't look to me that it is set on msvc. One
obvious consequence of that is that 64bit atomics won't be used (see
src/include/port/atomics/arch-arm.h) - but that shouldn't cause this issue.
Greetings,
Andres Freund