Peter Eisentraut <peter_e@gmx.net> writes:
> Tom Lane wrote:
>> But that code is gcc-only, and he's not using gcc.
> I think the icc compiler claims to be gcc-compatible in that area, so
> it's quite likely that the gcc assembler code would be used.
Oh, good point.
In that case it seems entirely possible that the assembly code
tightening-up patch that I made for 8.0 is relevant. The point of that
patch was to prevent the compiler from making inappropriate
optimizations around a spinlock TAS. We have not seen any indication
that existing gcc releases would actually do anything unwanted ... but
icc might have different/more aggressive optimizations.
[ looks at code... ] But it looks like 7.4's IA64 code already had the
memory-clobber constraint, so there doesn't appear to be any significant
change there since 7.4. I suppose it's worth trying the insignificant
change though:
__asm__ __volatile__(
" xchg4 %0=%1,%2 \n"
: "=r"(ret), "=m"(*lock)
: "r"(1), "1"(*lock)
: "memory");
to
__asm__ __volatile__(
" xchg4 %0=%1,%2 \n"
: "=r"(ret), "+m"(*lock)
: "r"(1)
: "memory");
at line 125ff of src/include/storage/s_lock.h. Note "=m" becomes "+m"
to replace the separate "1" constraint.
Robert, have you tried backing off compiler optimization levels to see
if anything changes?
regards, tom lane